1. Field of the Invention
This invention relates to a process for forming integrated circuit structures. More particularly, this invention relates to a process for filling spaces between metal lines with low k dielectric material to reduce capacitance between the metal lines.
2. Description of the Related Art
In the continuing reduction of scale in integrated circuit structures, both the width of metal interconnects or lines and the horizontal spacing between such metal lines on any particular level of such interconnects have become smaller and smaller. As a result, horizontal capacitance has increased between such conductive elements. This increase in capacitance, together with the vertical capacitance which exists between metal lines on different layers, results in loss of speed and increased cross-talk. As a result, reduction of such capacitance, particularly horizontal capacitance, has received much attention. One proposed approach to solving this problem of high capacitance is to replace the conventional silicon oxide (SiO2) dielectric material, having a dielectric constant (k) of about 4.0, with another dielectric material having a lower dielectric constant to thereby lower the capacitance.
In an article by L. Peters, entitled xe2x80x9cPursuing the Perfect Low-K Dielectricxe2x80x9d, published in Semiconductor International, Volume 21, No. 10, September 1998, at pages 64-74, a number of such alternate dielectric materials are disclosed and discussed. Included in these dielectric materials is a description of a low k dielectric material having a dielectric constant of about 3.0 formed using a chemical vapor deposition (CVD) process developed by Trikon Technologies of Newport, Gwent, U.K. The Trikon process is said to react methyl silane (CH3-SiH3) with hydrogen peroxide (H2O2) to form monosilicic acid which condenses on a cool wafer and is converted into an amorphous methyl-doped silicon oxide which is annealed at 400xc2x0 C. to remove moisture.
The use of low k carbon-doped silicon oxide dielectric material formed by reacting methyl silane with hydrogen peroxide (the Trikon process) has been found to have good gap filling characteristics, resulting in the formation of void-free filling of the high aspect ratio space between parallel closely spaced apart metal lines with dielectric material having a lower dielectric constant than that of convention silicon oxide, thereby resulting in a substantial lowering of the horizontal capacitance between such adjacent metal lines on the same metal wiring level.
However, the substitution of such low k carbon-doped silicon oxide dielectric materials formed by the Trikon process for conventional (non-low k) silicon oxide insulation has not been without its own problems. Formation of low k carbon doped silicon oxide dielectric material by the Trikon process is much slower than the conventional formation of undoped silicon oxide dielectric material. For example, in the time it takes to form a layer of low k carbon-doped silicon oxide dielectric material by the Trikon process on a single wafer, it may be possible to deposit a conventional silicon oxide dielectric layer of the same thickness on as many as 5 wafers.
However, even more importantly, it has been found that the subsequent formation of vias, or contact openings, through such low k carbon-doped silicon oxide dielectric material formed by the Trikon process to the underlying conductive portions such as metal lines, or contacts on an active device, can contribute to a phenomena known as via poisoning wherein filler material subsequently deposited in the via, such as a titanium nitride liner and tungsten filler material, fails to adhere to the via surfaces, apparently due to residues remaining from formation of the via in the particular low k dielectric material.
It has been proposed to solve the problem of via poisoning by forming such low k carbon-doped silicon oxide dielectric material by the Trikon process only between the metal lines, and then using a different dielectric material above the metal lines in the region of dielectric material through which vias will be formed down to the metal lines. Such a process is described and claimed in copending U.S. patent application Ser. No. 09/425,552 filed on Oct. 22, 1999 by two of us with another and assigned to the assignee of this application. The disclosure in that patent application is hereby incorporated herein by reference.
While termination of the height of a layer of Trikon process low k carbon-doped silicon oxide dielectric layer at the top of the metal lines inhibits the problem of via poisoning, the continued shrinkage of metal line widths and metal line spacing has given rise to the formation of borderless vias wherein the width of the via matches, or even exceeds the width of the metal line. This borderless via technology, coupled with possible misalignment of the via with the underlying metal line, can result in penetration of the via etch to dielectric levels below the top surface of the metal line, as shown in prior art FIG. 1.
In FIGS. 1A and 1B, a metal line 6 is shown formed over an integrated circuit structure 2, with a first low k dielectric material 10, such as the low k carbon-doped silicon oxide dielectric material formed by the Trikon process, shown formed adjacent the sides and up to the top of metal line 6. A layer of second low k dielectric material 12 is shown formed above first low k dielectric material 10. The layer of second low k dielectric material 12 comprises a PECVD-formed low k dielectric material which is more resistant to via poisoning.
When a via 14 is cut through second dielectric material 12, and the via 14 is misaligned with metal line 6, a portion of the via etch continues into first low k dielectric material 10 at the side of metal line 6, as shown at A. When via 14 extends down into first low k dielectric material 10 below the top of metal line 6, and the layer of first low k dielectric material 10 is formed by the Trikon process, problems similar to the aforementioned via poisoning can occur in this region.
It has also been proposed to deposit, in the regions between closely spaced apart metal lines, low k dielectric material formed by other processes such as by plasma enhanced chemical vapor deposition (PECVD), using CH4 and/or C4F8 and/or silicon tetrafluoride (SiF4) with a mixture of silane, O2, and argon gases. Plasma enhanced chemical vapor deposition (PECVD), in general, is described more fully by Wolf and Tauber in xe2x80x9cSilicon Processing for the VSLI Eraxe2x80x9d, Volume 1-Process Technology (1986), at pages 171-174. The use of such low k dielectric materials apparently does not result in the same via poisoning problems when exposed to etching. Furthermore, the formation of low k silicon oxide dielectric material such as low k carbon-doped silicon oxide dielectric material by PECVD is much faster than the formation of a layer of low k carbon-doped silicon oxide dielectric layer of the same thickness by the Trikon (i.e., at rates approaching the deposition rate of conventional silicon oxide).
However, low k silicon oxide dielectric material deposited by PECVD has poor gap filling characteristics in high aspect ratio regions, resulting in the formation of voids in dielectric materials deposited by PECVD in the spaces between the closely spaced apart metal lines in such structures. Such voids are undesirable because they may be inadvertently opened during subsequent processing, resulting in the trapping of etch residues and other difficult to remove materials in the subsequently opened voids.
It would, therefore, be highly desirable to provide a process for the formation of low k dielectric material adjacent closely spaced apart metal lines in an integrated circuit structure wherein the problems relating to borderless vias, misaligned vias, via poisoning, and void formation could be mitigated while providing the desired low k dielectric material adjacent the metal lines which results in reduction of the capacitance between the metal lines.
In a process for forming low k dielectric material between and over a plurality of spaced apart metal lines previously formed over a dielectric layer of an integrated circuit structure, the steps which include: depositing, over and between the plurality of metal lines, a first low k dielectric material resistant to via poisoning; then planarizing the layer of first low k dielectric material sufficiently to open voids formed in the first low k dielectric material between the metal lines; then depositing, over the layer of first low k dielectric material and. into the opened voids, a layer of second low k dielectric material capable of filling the opened voids in the layer of first low k dielectric material; and then depositing a third low k dielectric material resistant to via poisoning over the first low k dielectric material and the voids filled with second low k dielectric material.